View 1ED020I12FTA_436533.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Datasheet, Version 1.2, May 2010
EICEDRIVER(R)
1ED020I12FTA Single IGBT Driver IC
Power Management & Drives
Never
stop
thinking.
1ED020I12FTA Revision History: Previous Version: Page May 2010 2010-05-21 0 Version 1.2
Subjects (major changes since last revision)
Edition 2010-05-21 Published by Infineon Technologies AG, Campeon 1-12, 85579 Neubiberg, Germany (c) Infineon Technologies AG 2010. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
EICEDRIVER(R)
1ED020I12FTA
Single IGBT Driver IC
Product Highlights
* * * * * * Coreless transformer isolated driver Galvanic Insulation Integrated protection features Suitable for operation at high ambient temperature Automotive Qualified (pending) Two level turn off
Features
* * * * * Single channel isolated IGBT Driver For 600V/1200V IGBTs 2A rail-to-rail output Vcesat-detection Active Miller Clamp
Typical Application
* * * *
Input Side
Drive inverters for HEV and EV Auxilliary inverters for HEV and EV Inverters for electrical drives in CAV High Power DC/DC inverters
Output Side
VCC1
VCC2,H DESAT
IN+, IN-, /RST EiceDRIVERTM 1ED020I12FTA /FLT, RDY OUT CLAMP TLSET GND1 VEE2,H GND2,H CPU VCC2,L VCC1 DESAT IN+, IN-, /RST EiceDRIVERTM 1ED020I12FTA /FLT, RDY OUT CLAMP TLSET GND1 VEE2,L GND2,L
Figure 1: Type
Typical Application Gate drive current +/- 2A 1 Package PG-DSO-20-55 Version 1.2, 2010-05-21
1ED020I12FTA Preliminary Datasheet
EICEDRIVER(R) 1ED020I12FTA
Preliminary Datasheet
2
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
1 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.8 3 3.1 3.2 4 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 5 5.1 5.2 5.3 6 7 8 8.1 8.2
Block Diagram and Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READY status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Level Turn-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimal On Time / Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Miller Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 6 6 6 6 7 7 7 7 8 8 8 8 8
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-level Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . According to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation . . . . . . . . . . . . . . . . . . . . . . . According to UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 13 14 14 14 16 16 16 17 18 18 18 19 19 19 19
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Prelim Datasheet
3
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Prelim Datasheet
4
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Block Diagram and Application
1
Block Diagram and Application
VCC1
18
UVLO &
UVLO
K4 2V
6
VCC2
IN+
13
1 VCC1
delay delay
8 TX RX &
VCC2 20MHz VEE2
CLAMP
IN-
14
VCC1
OSC
& 7
OUT
RDY
15 &
1 VCC1 FLTNL RDY2 /RDY
DECODER
RX
TX
ENCODER
VCC2 500A
VEE2 250
FLT2 7V
5
TLSET
/FLT
16 &
1 VCC1 FLT
& & 1
K3 9V
VCC2 250A
Q
S R
3
250 1k
DESAT
1
/RST
17
delay
1
RST VEE2
4 9 10
GND2
11
GND1
12
GND1
1
19
GND1
20
GND1
1ED020I12FTA
1
2
Figure 1:
Block Diagram 1ED020I12FTA
+5V
10k 10k
10R 100n
VCC1
VCC2 DESAT
+15V
1 1k
SGND IN+ RDY FLT RS
GND1 CLAMP IN+ INRDY /FLT /RST VEE2 OUT TLSET 10R
10V
10p
100p
GND2 1
-8V
1ED020I12FTA
Figure 2:
Application Example 5 Version 1.2, 2010-05-21
Preliminary Datasheet
EICEDRIVER(R) 1ED020I12FTA
Functional Description
2
2.1
Functional Description
Introduction
The 1ED020I12FTA is an advanced IGBT gate driver for motor drives typical greater 10kW. Control and protection functions are included to make possible the design of high reliability systems. The device consists of two galvanic separated parts. The input chip can be directly connected to a standard 5V DSP or microcontroller with CMOS in/output and the output chip is connected to the high voltage side. An effective active Miller clamp function avoids the need of negative gate driving in some applications and allows the use of a simple bootstrap supply for the high side driver. A rail-to-rail driver output enables the user to provide easy clamping of the IGBTs gate voltage during short circuit of the IGBT. So an increase of short circuit current due to the feedback via the Miller capacitance can be avoided. Further, a rail-to-rail output reduces power dissipation. The device also includes an IGBT desaturation protection with a FAULT status output. A two-level turn-off feature with adjustable delay protects against excessive overvoltage at turn-off in case of overcurrent or short circuit condition. The same delay is applied at turn-on to prevent pulse width distortion. A READY status output reports if the device is supplied and operates correctly.
2.2 2.2.1
Internal Protection Features Undervoltage Lockout (UVLO)
To ensure correct switching of IGBTs the device is equipped with an undervoltage lockout for both chips. If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output chip before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored as long as VVCC1 reaches the power-up voltage VUVLOH1 . If the power supply voltage VVCC2 of the output chip goes down below VUVLOL2 the IGBT is switched off and signals from the input chip are ignored as long as VVCC2 reaches the power-up voltage VUVLOH2 .
2.2.2
* * *
READY status output
The READY output at pin /RDY shows the status of three internal protection features. UVLO of the input chip UVLO of the output chip after a short delay Internal signal transmission
It is not necessary to reset the READY signal since its state only depends on the status of the former mentioned protection signals.
2.2.3
Watchdog Timer
The 1ED020I12FA incorporates two levels of protection to ensure signal integrity by two independent watchdog timers. First level ensures the short term signal integrity by resending the (turn on/off) signals with a watchdog period of typical 500ns. The second level monitors the internal signal transmission during normal operation. If the transmission fails for a given time, the IGBT is switched off and the READY output reports an internal error.
2.2.4
Active Shut-Down
The Active Shut-Down feature ensures a safe IGBT off-state if the output chip is not connected to the power supply.
Preliminary Datasheet
6
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Functional Description
2.3
Non-Inverting and Inverting Inputs
There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output while IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high. A minimum input pulse width is defined to filter occasional glitches.
2.4
Driver Output
The output driver section uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight control of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is stable. Due to the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by the gate resistor. Furthermore, it reduces the power to be dissipated by the driver.
2.5
Two-Level Turn-Off
The Two-Level Turn-OFF introduces a second turn off voltage level at the driver output in between ON- and OFFlevel. This additional level ensures lower VCE overshoots at turn off by reducing gate emitter voltage of the IGBT at short circuits or over current events. The VGE level is adjusting the current of the IGBT at the end two level turn off interval, therequired timing is depending on stray inductance and over current at beginning of two level turn off interval. Reference voltage level and hold up time could be adjusted at TLSET pin. The reference voltage is set by the required Zener diode connected between pin TLSET and GND2. The hold up time is set by the capacitor connected to the same pin TLSET and GND2. The hold time can be adjusted during switch on using the whole capacitance connected at pin TLSET including capacitor, parasitic wiring capacitance and junction capacitance of Zener diode. When a switch on signal is given the IC starts to discharge CTLSET. Discharging CTLSET is stopped after 500nsec. Then Ctlset is charged with an internal charge current Itlset. When the voltage of the capacitor Ctlset exceeds 7V a second current source starts charging Ctlset up to VZDIODE. At the end of this discharge-charge cycle the gate driver is switched on. The time between IN initiated switch-on signal (minus an internal propagation delay of approximately 200ns) and switch-on of the gate drive is sampled and stored digitally. It represents the two level turn off set time TTLSET during switch-off. Due to digitalization the tpdon time can vary in time steps of 50nsec. If switch off is initiated from IN+, IN- or /RST signal, the gate driver is switched off immediately after internal propagation delay of approximately 200ns and VOUT begins to decrease. For switch off initiated by DESAT, the gate driver switch off is delayed by desaturation sense to OUT delay. The output voltage VOUT is sensed and compared with the Zener voltage VZDIODE. When VOUT falls below the reference voltage VZDIODE of the Zener diode the switch off process is interrupted and Vout is adjusted to VZDIODE. OUT is switched to VEE2 after the hold up time has passed. The Two-Level Turn-OFF function can not be disabled.
2.6
Minimal On Time / Off Time
The 1ED020I12FTA driver requires minimal on and off time for propper operation in the application. Minimal on time must be greater than the adjustable two level plateau time TTLSET, shorter on times will be surpressed by generating of the plateau time. Due to the short on time, the voltage at TLSET pin does not reach the comparator threshold, therefore the driver do not turn on. A similar principle takes place for off time. Minimal off time must be greater than TTLSET, shorter off times will be surpressed, which means OUT stays on. A two level turn off plateau can not be shortened by the driver. If the driver has entered the turn off sequence it can not switch off due to the fact, that the driver has already entered the shut off mode. But if the driver input signal is turned on again, it will leave the lower level after TTLSET time by switching OUT to high.
Preliminary Datasheet
7
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Functional Description
2.7 2.7.1
External Protection Features Desaturation Protection
A desaturation protection ensures the protection of the IGBT at short circuit. When the DESAT voltage goes up and reaches 9V, the output is driven low. Further, the FAULT output is activated. A programmable blanking time is used to allow enough time for IGBT saturation. Blanking time is provided by a highly precise internal current source and an external capacitor.
2.7.2
Active Miller Clamping
A Miller clamp allows sinking the Miller current during a high dV/dt situation. Therefore, the use of a negative supply voltage can be avoided in many applications. During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2V (related to VEE2). The clamp is designed for a Miller current up to 2A.
2.7.3
Short Circuit Clamping
During short circuit the IGBTs gate voltage tends to rise because of the feedback via the Miller capacitance. An additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than the supply voltage. A current of maximum 500 mA for 10us may be fed back to the supply through one of this paths. If higher currents are expected or a tighter clamping is desired external Schottky diodes may be added.
2.8
RESET
The reset input has two functions. Firstly, /RST is in charge of setting back the FAULT output. If /RST is low longer than a given time , /FLT will be reseted at the rising edge of /RST; otherwise, it will remain unchanged. Moreover, it works as enable/shutdown of the input logic.
Preliminary Datasheet
8
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Pin Configuration and Functionality
3
3.1
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Configuration and Functionality
Pin Configuration
Symbol VEE2 VEE2 DESAT GND2 TLSET VCC2 OUT CLAMP VEE2 VEE2 GND1 GND1 IN+ INRDY FLT RST VCC1 GND1 GND1 Function Negative power supply output side Negative power supply output side Desaturation protection Signal ground output side Two level set Positive power supply output side Driver output Miller clamping Negative power supply output side Negative power supply output side Signal ground input side Signal ground input side Non inverted driver input Inverted driver input Ready output Fault output, low active Reset input, low active Positive power supply input side Signal ground input side Signal ground input side
1 2 3 4 5 6 7 8 9
VEE2 VEE2 DESAT GND2 TLSET VCC2 OUT CLAMP VEE2
GND1 20 GND1 19 VCC1 18 /RST 17 /FLT 16 RDY 15 IN- 14 IN+ 13 GND1 12 GND1 11
10 VEE2
Figure 3:
Pin Configuration PG-DSO-20-55 (top view)
Preliminary Datasheet
9
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Pin Configuration and Functionality
3.2
GND1
Pin Functionality
Ground connection of the input side. IN+ Non-inverting driver input IN+ control signal for the driver output if IN- is set to low. (The IGBT is on if IN+ = high and IN- = low) A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor ensures IGBT Off-State. IN- Inverting driver input IN- control signal for driver output if IN+ is set to high. (IGBT is on if IN- = low and IN+ = high) A minimum pulse width is defined to make the IC robust against glitches at IN-. An internal Pull-Up-Resistor ensures IGBT Off-State. /RST (Reset) input Function 1: Enable/shutdown of the input chip. (The IGBT is off if /RST = low). A minimum pulse width is defined to make the IC robust against glitches at IN-. Function 2: Resets the DESAT-FAULT-state of the chip if /RST is low for a time TRST. An internal Pull-Up-Resistor is used to ensure FLT status output. /FLT (Fault output) Open-drain output to report a desaturation error of the IGBT (FLT is low if desaturation occurs) RDY (Ready status) Open-drain output to report the correct operation of the device. (RDY = high if both chips are above the UVLO level and the internal chip transmission is faultless) VCC1 5V power supply of the input chip VEE2 Negative power supply pins of the output chip. If no negative supply voltage is available, all VEE2 pins have to be connected to GND2. DESAT (Desaturation) Monitoring of the IGBT saturation voltage (VCE) to detect desaturation caused by short circuits. If OUT is high, VCE is above a defined value and a certain blanking time has expired, the desaturation protection is activated and the IGBT is switched off. The blanking time is adjustable by an external capacitor. CLAMP (Clamping) Ties the gate voltage to ground after the IGBT has been switched off at a defined voltage to avoid a parasitic switch-on of the IGBT.During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2V (related to VEE2). GND2 Reference ground of the output chip.
Preliminary Datasheet
10
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Pin Configuration and Functionality OUT (Driver output) Output pin to drive an IGBT. The voltage is switched between VEE2 and VCC2. In normal operating mode Vout is controlled by IN+, IN- and /RST. During error mode (UVLO, internal error or DESAT) Vout is set to VEE2 independent of the input control signals. VCC2 Positive power supply pin of the output side. TLSET (Two-Level turn-off) Setting up the timing (with ext. capacitor) and voltage reference (with ext. Zener diode) for the two-level turn-off, see figure 5.
Preliminary Datasheet
11
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Electrical Parameters
4
4.1
Electrical Parameters
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. Unless otherwise noted all parameters refer to GND1. Parameter Positive power supply output side Negative power supply output side Maximum power supply voltage output side (VVCC2-VVEE2) Gate driver output Gate driver high output maximum current Gate driver low output maximum current Maximum short circuit clamping time Positive power supply input side Logic input voltages (IN+,IN-,RST) Opendrain Logic output voltage (FLT) Opendrain Logic output voltage (RDY) Opendrain Logic output current (FAULT) Opendrain Logic output current (RDY) Pin DESAT voltage Pin TLSET voltage Pin CLAMP voltage Junction temperature Storage temperature Power dissipation, Input chip Power dissipation, Output chip Thermal resistance (Input chip active) Thermal resistance (Output chip active) ESD Capability
1) With respect to GND2. 2) may be exceeded during short circuit clamping 3) Output IC power dissipation is derated linearly at 8.5 mW/C above 68C. Input IC power dissipation does not require derating. See section 8.1 for reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation of components in close proximity. 4) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor).
Symbol VVCC2 VVEE2 Vmax2 VOUT IOUT IOUT tCLP VVCC1 VLogicIN VFLT VRDY IFLT IRDY VDESAT VTLSET VCLAMP TJ TS PD, IN PD, OUT RTHJA,IN RTHJA,OUT VESD
Limit Values min. -0.3 -12 max. 20 0.3 28 Vmax2+0.3 2.4 2.4
Unit Remarks V V V V A A us V V V V mA mA
1) 1) 1) 1)
VVEE2-0.3
t = 2s t = 2s ICLAMP/OUT = 500mA
-0.3 -0.3 -0.3 -0.3
10 6.5 6.5 6.5 6.5 10 10 VVCC2 +0.3 VVCC2 +0.3 VVCC2+0.3
2)

-0.3 -0.3 VVEE2-0.3 -40 -55
VVEE2 = -8V VVEE2 = -8V
150 150 100 700 139 117 1.5
C C mW mW K/W K/W kV
3)

@TA = 25 @TA = 25 @TA = 25C @TA = 25C
2)3) 2) 2)
Human Body Model4)
Preliminary Datasheet
12
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Electrical Parameters
4.2
Operating Parameters
Note: Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND1. Parameter Positive power supply output side Negative power supply output side Maximum power supply voltage output side (VVCC2-VVEE2) Positive power supply input side Logic input voltages (IN+,IN-,RST) Pin CLAMP voltage Pin DESAT voltage Pin TLSETvoltage Ambient temperature Common mode transient immunity
1) With respect to GND2. 2) May be exceeded during short circuit clamping 3) The parameter is not subject to production test - verified by design/characterization
3)
Symbol VVCC2 VVEE2 Vmax2 VVCC1 VLogicIN VCLAMP VDESAT VTLSET TA |VISO/dt|
Limit Values min. 13 -12 max. 20 0 28 5.5 5.5 VVCC22) VVCC2 VVCC2 125 50
Unit V V V V V V V V C
Remarks
1) 1)
4.5 -0.3 VVEE2-0.3 -0.3 -0.3 -40 --
1) 1)
kV/s @ 500V
4.3
Parameter
Recommended Operating Parameters
Symbol VVCC2 VVEE2 VVCC1 Values 15 -8 5 Unit V V V Remarks
1) 1)
Note: Unless otherwise noted all parameters refer to GND1.
Positive power supply output side Negative power supply output side Positive power supply input side
1) With respect to GND2.
Preliminary Datasheet
13
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Electrical Parameters
4.4
Electrical Characteristics
Note: The electrical characteristics include the spread of values in supply voltages, load and junction temperatures given below. Typical values represent the median values at TA = 25C. Unless otherwise noted all voltages are given with respect to their respective GND (GND1 for pins 11 to 20, GND2 for pins 1 to 10).
4.4.1
Parameter
Voltage Supply.
Symbol VUVLOH1 VUVLOL1 3.5 0.15 VHYS1 VUVLOH2 VUVLOL2 VHYS2 IQ1 0.7 Limit Values min. typ. 4.1 3.8 max. 4.3 V Unit Test Conditions
UVLO Threshold Input Chip UVLO Hysteresis Input Chip (VUVLOH1 - VUVLOL1) UVLO Threshold Output Chip UVLO Hysteresis Output Chip (VUVLOH1 - VUVLOL1) Quiescent Current Input Chip
12.0 11.0 0.9

12.6
V V V V V mA VVCC1 =5V IN+ = High, IN- = Low =>OUT = High, RDY = High, /FLT = High VVCC2 =15V VVEE2 =-8V IN+ = High, IN- = Low =>OUT = High, RDY = High, /FLT = High
10.4

9
7
Quiescent Current Output Chip
IQ2
4.5
6
mA
4.4.2
Parameter
Logic Input and Output
Symbol VIN+L,VINVIN+H,VIN- 3.5 Limit Values min. typ. max. 1.5 V Unit Test Conditions
IN+,IN-, RST Low Input Voltage IN+,IN-, RST High Input Voltage IN-, RST Input Current IN+ Input Current RDY,FLT Pull Up Current Input Pulse Suppression IN+, INInput Pulse Suppression RST for ENABLE/SHUTDOWN Pulse Width RST for Reseting FLT FLT Low Voltage RDY Low Voltage
L,VRSTL HVRSTH

400 400 400
V uA uA uA VIN-=GND1 VRST =GND1 VIN+=VCC1 VRDY=GND1 VFLT=GND1
IIN-,IRST IIN+, IPRDY, IPFLT TMININ+, TMININTMINRST TRST VFLTL VRDYL 30 30 800

100 100 100 40 40

300 300
ns ns ns mV mV ISINK(FLT) = 5mA ISINK(RDY) = 5mA Version 1.2, 2010-05-21

14

Preliminary Datasheet
EICEDRIVER(R) 1ED020I12FTA
Electrical Parameters
4.4.3
Parameter
Gate Driver
Symbol min. VOUTH1 VOUTH2 VOUTH3 VOUTH4 VVCC2-1.2 VVCC2-2.5 VVCC2-9 -1.5 Limit Values typ. VVCC2-0.8 VVCC2-2.0 VVCC2-5 VVCC2-10 -2.0 VVEE2+0.04 VVEE2+0.3 VVEE2+2.1 VVEE2+7 2.0 max. Unit Test Conditions
High Level Output Voltage
High Level Output Peak Current Low Level Output Voltage
IOUTH VOUTL1 VOUTL2 VOUTL3 VOUTL4

VVEE2+0.09 VVEE2+0.85 VVEE2+5.0 -- --
V V V V A V V V V A
IOUTH = -20mA IOUTH = -200mA IOUTH = -1A IOUTH = -2A IN+ = High, IN- = Low; OUT = High IOUTL = 20mA IOUTL = 200mA IOUTL = 1A IOUTL = 2A IN+ = Low, IN- = Low; OUT = Low, VVCC2 =15V, VVEE2 =-8V

1.5
Low Level Output Peak Current
IOUTL
4.4.4
Parameter
Active Miller Clamp
Symbol min. VCLAMPL1 VCLAMPL2 VCLAMPL3 Limit Values typ. VVEE2+0.3 VVEE2+1.9 2 1.6 max. IOUTL = 20mA IOUTL = 200mA IOUTL = 1A
1)
Unit Test Conditions
Low Level Clamp Voltage
VVEE2+0.03 VVEE2 +0.08 V VVEE2 +0.8 VVEE2 +4.8 V V A V
Low Level Clamp Current Clamp Threshold Voltage
ICLAMPL VCLAMP
2.1
2.4
Related to VEE2
1) The parameter is not subject to production test - verified by design/characterization
4.4.5
Parameter
Short Circuit Clamping
Symbol VCLPout Limit Values min. typ. 0.8 max. 1.3 V IN+=High, IN-=Low, OUT=High IOUT = 500mA (pulse test,tCLPmax=10us) IN+=High, IN-=Low, OUT=High ICLAMP = 500mA (pulse test,tCLPmax=10us) IN+=High, IN-=Low, OUT=High ICLAMP = 20mA Unit Test Conditions
Clamping voltage (OUT) (VOUT-VVCC2)
Clamping voltage (CLAMP) (VVCLAMP-VVCC2)
VCLPclamp
1.3
V
Clamping voltage (CLAMP)
VCLPclamp
0.7
1.1
V
Preliminary Datasheet
15
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Electrical Parameters
4.4.6
Parameter
Dynamic Characteristics
Symbol TPDON TPDISTO Limit Values min. typ. 1.8 30 1.8 30 1.9 40 1.9 40 1.8 20 1.8 20 30 max. 2.1 60 tbd 2.81) 60 2.3 70 tbd 3.01) 70 2.3 50 tbd 3.01) 50 60 us ns us ns us ns us ns us ns us ns ns CTLSET=0, TA=25C CTLSET=0, TA=25C CTLSET=0, TA=25C CTLSET=0, TA=25C CTLSET=0, TA=125C CTLSET=0, TA=125C CTLSET=0, TA=125C CTLSET=0, TA=125C CTLSET=0, @TA=-40C CTLSET=0, @TA=-40C CTLSET=0, @TA=-40C CTLSET=0, @TA=-40C VVCC2 =15V,VVEE2 =-8V CLOAD= 1nF, VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 34nF VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 1nF VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 34nF VL 10% ,VH 90% 1.6 0 1.6 tbd -5451) 1.5 0 1.5 tbd -7001) 1.5 0 1.5 tbd -7001) 10 Unit Test Conditions
IN+ Input to output propagation delay ON/OFF and IN- OFF IN+ Input to output propagation delay distortion (TPDOFF-TPDON)
IN- Input to output propagation delay ON TPDONIN- Input to output propagation delay distortion (TPDOFF-TPDON) IN+ Input to output propagation delay ON/OFF and IN- OFF IN+ Input to output propagation delay distortion (TPDOFF-TPDON) TPDISTOTPDONt TPDISTOt
IN- Input to output propagation delay ON TPDON-t IN- Input to output propagation delay distortion (TPDOFF-TPDON) IN+ Input to output propagation delay ON/OFF and IN- OFF IN+ Input to output propagation delay distortion (TPDOFF-TPDON) TPDISTO-t TPDONt TPDISTOt
IN- Input to output propagation delay ON TPDON-t IN- Input to output propagation delay distortion (TPDOFF-TPDON) Rise Time TPDISTO-t TRISE
150
400
800
ns
Fall Time
TFALL
10
20
40
ns
100
250
500
ns
1) The maximum value of input to output propagation delay ON at IN- occures only in case of electromagnetic interferences, typically the input to output delay is 2.1s at TA =25C, one worst case watchdog clock cycle shorter (see chapter 2.2.3). The turn OFF-signal is prioritized/dominant and will not show up this behavior.
Preliminary Datasheet
16
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Electrical Parameters
4.4.7
Parameter
Desaturation protection
Symbol IDESATC IDESATD VDESAT VDESAT TDESATOUT TDESATFLT VDESATL Limit Values min. typ. 500 15 9 9 270 max. 550 uA VVCC2 =15V,VVEE2 =-8V VDESAT=2V 450 11 8.5 8.5 Unit Test Conditions
Blanking Capacitor Charge Current Blanking Capacitor Discharge Current Desaturation Reference Level Desaturation Reference Level Desaturation Sense to OUT TLTO Desaturation Sense to FLT Low Delay Desaturation Low Voltage
9.5 9.5 320 2.25
mA VVCC2 =15V,VVEE2 =-8V VDESAT=6V V V ns us VVCC2 =15V,VVEE2 =-8V VVCC2 =15V,VVEE2 =0V VOUT =90% CLOAD= 1nF VFLT =10%; IFLT =5mA

40
70
110
mV IN+=Low, IN-=Low, OUT=Low
4.4.8
Parameter
Active Shut Down
Symbol VACTSD
1)
Limit Values min. typ. max. 2.0
Unit Test Conditions
Active Shut Down Voltage
1) With reference to VEE2
V
IOUT=-200mA, VCC2 open
4.4.9
Parameter
Two-level Turn-off
Symbol Limit Values min. typ. max. VCC2-0.5 V 7.3 550 V uA VTLSET=10V 7.5 6.6 420 Unit Test Conditions
External reference voltage range (Zener- VZDIODE Diode) Reference Voltage for setting two-level delay time Current for setting two-level delay time and external reference voltage (ZenerDiode) External Capacitance Range VTLSET ITLSET
7 500
CTLSET
0
220
pF
Preliminary Datasheet
17
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Insulation Characteristics
5
5.1
Description
Insulation Characteristics
Complies with DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation
Symbol Characteristic I-IV I-III I-II 40/125/21 2 CLR CPG CTI VIORM VIOTM VIOSM 8 8 175 1420 6000 6000 VPEAK VPEAK V mm mm Unit
Installation classification per EN 60664-1, Table 1 for rated mains voltage 150 VRMS for rated mains voltage 300 VRMS for rated mains voltage 600 VRMS Climatic Classification Pollution Degree (EN 60664-1) Minimum External Clearance Minimum External Creepage Minimum Comparative Tracking Index Maximum Repetitive Insulation Voltage Highest Allowable Overvoltage
1)
Maximum Surge Insulation Voltage
5.2
Description
According to UL 1577
Symbol VISO VISO Characteristic 3750 4500 Unit Vrms Vrms
Insulation Withstand Voltage / 1min Insulation Test Voltage / 1sec
5.3
Reliability
For Qualification Report please contact your local Infineon Technologies office.
Preliminary Datasheet
18
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Timing Diagrams
6
Timing Diagrams
All diagrams related to the Two-level switch-off feature
IN+
V ZDIODE
TLSET
TPD TADJ 1 TTLSET TPD TTLFALL TPDONADJ
VTLSET , typ. 7V
V ZDIODE
OUT
TTLSET
Figure 4:
Typical Switching Behavior
IN+
TPDON
OUT
TDESATOUT VDESAT typ. 9V
TTLSET TDESATOUT
TTLSET
DESAT
/FLT
TDESATFLT TDESATFLT
/RST
>TRSTmin
Figure 5:
DESAT Switch-OFF Behavior
Preliminary Datasheet
19
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Timing Diagrams
IN+ TLSET
TPD
TPD
TTLSET
TTLSET
OUT
Figure 6: Short Switch ON Pulses
TPDON TTLSET
TPDON TPDOFF
IN+ TLSET
TPD TTLSET TTLSET TPD TTLSET TPDON
OUT
Figure 7:
TPDOFF
TPDON
TPDOFF
TPDOFF
Short Switch OFF Pulses
IN+ TLSET
TPD TTLSET
TTLSET
TTLSET
TTLSET TPD
OUT
TPDON
TPDOFF
TPDOFF
TPDOFF
TPDON
forced turn off after three consecutive on -cycles
Figure 8:
Short Switch OFF Pulses, Ringing Surpression
Preliminary Datasheet
20
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Timing Diagrams
VUVLOH2
VCC2 IN+
OUT I DESAT RDY
Figure 9: VCC2 Ramp Up
TPDON
TPDOFF
VCC2
VUVLOH2 VUVLOL2 TPDD TPDD TPDD
IN+ TLSET
Vz
TTLSET
OUT RDY /FLT
TPDON
Figure 10: VCC2 Ramp Down and VCC2 Drop
Preliminary Datasheet
21
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Timing Diagrams
5 4
TTLSET [usec]
3 2 1 0
0
50
100
150
200
C TLSET [pF]
Figure 11: Typical TTLSET Time over CTLSET Capacitance
Preliminary Datasheet
22
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Package Outlines
7
Package Outlines
PG-DSO-20-55 (Plastic Dual Small Outline Package)
Figure 12: PG-DSO-20-55
Preliminary Datasheet
23
Version 1.2, 2010-05-21
EICEDRIVER(R) 1ED020I12FTA
Application Notes
8
8.1
Application Notes
Reference Layout for Thermal Data
The PCB layout shown in figure 12 represents the reference layout used for the thermal characterisation. Pins 11, 12, 19 and 20 (GND1) and pins 1, 2, 9 and 10 (VEE2) require ground plane connections for achiving maximum power dissipation. The 1ED020I12FTA is conceived to dissipate most of the heat generated through this pins.
PCB + Top-Layer
PCB + Bottom-Layer
Figure 13: Reference layout for thermal data (Copper thickness 102mm)
8.2
Printed Circuit Board Guidelines
Following factors should be taken into account for an optimum PCB layout. - Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits. - The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained to increase the effective isolation and reduce parasitic coupling. - In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept as short as possible.
Preliminary Datasheet
24
Version 1.2, 2010-05-21
www.infineon.com/gatedriver
Published by Infineon Technologies AG

▲Up To Search▲

Price & Availability of 1ED020I12FTA

	To Download 1ED020I12FTA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .